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quad, 12-/14-/16-bit nano dacs with 5 ppm/c on-chip reference ad5624r/ad5644r/ad5664r rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2008 analog devices, inc. all rights reserved. features low power, smallest pin-compatible, quad nano dacs ad5664r: 16 bits ad5644r: 14 bits ad5624r: 12 bits user-selectable external or internal reference external reference default on-chip 1.25 v/2.5 v, 5 ppm/c reference 10-lead msop and 3 mm 3 mm lfcsp_wd 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale per channel power-down serial interface, up to 50 mhz applications process controls data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators functional block diagram 0 5856-001 buffer buffer ad5624r/ad5644r/ad5664r 1.25v/2.5v ref v dd v refin / v refout gnd power- down logic power-on logic sclk s ync din string dac a string dac b string dac c string dac d dac register dac register dac register dac register input register input register input register input register interface logic buffer buffer v out a v out b v out c v out d figure 1. table 1. related devices part no. description ad5624 / ad5664 2.7 v to 5.5 v quad, 12-/16-bit dacs, external reference ad5666 2.7 v to 5.5 v quad, 16-bit dac, internal reference, ldac , clr pins general description the ad5624r/ad5644r/ad5664r, members of the nano dac? family, are low power, quad, 12-/14-/16-bit buffered voltage-out dacs. all devices operate from a single 2.7 v to 5.5 v supply and are guaranteed monotonic by design. the ad5624r/ad5644r/ad5664r have an on-chip reference. the ad56x4r-3 has a 1.25 v, 5 ppm/c reference, giving a full- scale output range of 2.5 v; the ad56x4r-5 has a 2.5 v, 5 ppm/c reference giving a full-scale output range of 5 v. the on-chip reference is off at power-up, allowing the use of an external refer- ence; all devices can be operated from a single 2.7 v to 5.5 v supply. the internal reference is enabled via a software write. the part incorporates a power-on reset circuit that ensures the dac output powers up to 0 v and remains there until a valid write takes place. the part contains a per-channel power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power-down mode. the low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. the ad5624r/ad5644r/ad5664r use a versatile 3-wire serial interface that operates at clock rates up to 50 mhz, and is com- patible with standard spi, qspi?, microwire?, and dsp interface standards. the on-chip precision output amplifier enables rail-to-rail output swing. product highlights 1. quad 12-/14-/16-bit dacs. 2. on-chip 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 10-lead msop and 10-lead, 3 mm 3 mm, lfcsp_wd. 4. low power, typically consumes 1.32 mw at 3 v and 2.25 mw at 5 v.
ad5624r/ad5644r/ad5664r rev. b | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ad5624r-5/ad5644r-5/ad5664r-5 ....................................... 3 ? ad5624r-3/ad5644r-3/ad5664r-3 ....................................... 4 ? ac characteristics ........................................................................ 6 ? timing characteristics ................................................................ 7 ? timing diagram ........................................................................... 7 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 18 ? theory of operation ...................................................................... 20 ? digital-to-analog section ......................................................... 20 ? resistor string ............................................................................. 20 ? output amplifier ........................................................................ 20 ? internal reference ...................................................................... 20 ? external reference ..................................................................... 20 ? serial interface ............................................................................ 20 ? input shift register .................................................................... 21 ? sync interrupt ........................................................................... 21 ? power-on reset .......................................................................... 22 ? software reset ............................................................................. 22 ? power-down modes .................................................................. 22 ? ldac function ........................................................................... 23 ? internal reference setup ........................................................... 23 ? microprocessor interfacing ....................................................... 24 ? applications ..................................................................................... 25 ? using a reference as a power supply for the ad5624r/ad5644r/ad5664r ............................................... 25 ? bipolar operation using the ad5624r/ad5644r/ad5664r ............................................... 25 ? using ad5624r/ad5644r/ad5664r with a galvanically isolated interface ........................................................................ 25 ? power supply bypassing and grounding ................................ 26 ? outline dimensions ....................................................................... 27 ? ordering guide .......................................................................... 28 ? revision history 4/08rev. a to rev. b changes to figure 50 ...................................................................... 20 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 11/06rev. 0 to rev. a changes to reference output parameter in table 2 .................... 3 changes to reference output parameter in table 3 .................... 5 added note to figure 3 .................................................................... 9 4/06revision 0: initial version
ad5624r/ad5644r/ad5664r rev. b | page 3 of 28 specifications ad5624r-5/ad5644r-5/ad5664r-5 v dd = 4.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 2. b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5664r resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5644r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad5624r resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-code error 2 10 mv all zeroes loaded to dac register offset error 1 10 mv full-scale error ?0.1 1 % of fsr all ones loaded to dac register gain error 1.5 % of fsr zero-code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale; v dd = 5 v 10% dc crosstalk external reference 10 v due to full-scale output change, r l = 2 k to gnd or v dd 10 v/ma due to load current change 5 v due to powering down (per channel) internal reference 25 v due to full-scale output change, r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short-circuit current 30 ma v dd = 5 v power-up time 4 s coming out of power-down mode; v dd = 5 v reference inputs reference current 170 200 a v ref = v dd = 5.5 v reference input range 0.75 v dd v reference input impedance 26 k reference output output voltage 2.495 2.505 v at ambient reference tc 3 5 10 ppm/c msop package models 10 ppm/c lfcsp package models output impedance 7.5 k
ad5624r/ad5644r/ad5664r rev. b | page 4 of 28 b grade 1 parameter min typ max unit conditions/comments logic inputs 3 input current 2 a all digital inputs v inl , input low voltage 0.8 v v dd = 5 v v inh , input high voltage 2 v v dd = 5 v pin capacitance 3 pf power requirements v dd 4.5 5.5 v i dd v ih = v dd , v il = gnd, v dd = 4.5 v to 5.5 v normal mode 4 0.45 0.9 ma internal reference off 0.95 1.2 ma internal reference on all power-down modes 5 0.48 1 a 1 temperature range: b grade: ?40c to +105c. 2 linearity calculated using a reduced code range: ad5664r (code 512 to code 65,024); ad 5644r (code 128 to code 16,256); ad5624r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down. ad5624r-3/ad5644r-3/ad5664r-3 v dd = 2.7 v to 3.6 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 3. b grade 1 parameter min typ max unit conditions/comments static performance 2 ad5664r resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad5644r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad5624r resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero-code error 2 10 mv all zeroes loaded to dac register offset error 1 10 mv full-scale error ?0.1 1 % of fsr all ones loaded to dac register gain error 1.5 % of fsr zero-code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ?100 db dac code = midscale; v dd = 3 v 10% dc crosstalk external reference 10 v due to full-scale output change, r l = 2 k to gnd or v dd 10 v/ma due to load current change 5 v due to powering down (per channel) internal reference 25 v due to full-scale output change, r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel)
ad5624r/ad5644r/ad5664r rev. b | page 5 of 28 b grade 1 parameter min typ max unit conditions/comments output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short-circuit current 30 ma v dd = 3 v power-up time 4 s coming out of power-down mode; v dd = 3 v reference inputs reference current 170 200 a v ref = v dd = 3.6 v reference input range 0 v dd v reference input impedance 26 k reference output output voltage 1.247 1.253 v at ambient reference tc 3 5 15 ppm/c msop package models 10 ppm/c lfcsp package models output impedance 7.5 k logic inputs 3 input current 2 a all digital inputs v inl , input low voltage 0.8 v v dd = 3 v v inh , input high voltage 2 v v dd = 3 v pin capacitance 3 pf power requirements v dd 2.7 3.6 v i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 3.6 v normal mode 4 0.44 0.85 ma internal reference off 0.95 1.15 ma internal reference on all power-down modes 5 0.2 1 a 1 temperature range: b grade: ?40c to +105c. 2 linearity calculated using a reduced code range: ad5664r (code 512 to code 65,024); ad 5644r (code 128 to code 16,256); ad5624r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization, not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down.
ad5624r/ad5644r/ad5664r rev. b | page 6 of 28 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. 1 table 4. parameter 2 min typ max unit conditions/comments 3 output voltage settling time ad5624r 3 4.5 s ? to ? scale settling to 0.5 lsb ad5644r 3.5 5 s ? to ? scale settling to 0.5 lsb ad5664r 4 7 s ? to ? scale settling to 2 lsb slew rate 1.8 v/s digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry digital feedthrough 0.1 nv-s reference feedthrough ?90 db v ref = 2 v 0.1 v p-p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv-s analog crosstalk 1 nv-s external reference 4 nv-s internal reference dac-to-dac crosstalk 1 nv-s external reference 4 nv-s internal reference multiplying bandwidth 340 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?80 db v ref = 2 v 0.1 v p-p, frequency = 10 khz output noise spectral density 120 nv/hz dac code = midscale, 1 khz 100 nv/hz dac code = midscale, 10 khz output noise 15 v p-p 0.1 hz to 10 hz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typi cal at 25c.
ad5624r/ad5644r/ad5664r rev. b | page 7 of 28 timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2 (see figure 2 ). v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. 1 table 5. limit at t min , t max parameter v dd = 2.7 v to 5.5 v unit conditions/comments t 1 2 20 ns min sclk cycle time t 2 9 ns min sclk high time t 3 9 ns min sclk low time t 4 13 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 15 ns min minimum sync high time t 9 13 ns min sync rising edge to sclk fall ignore t 10 0 ns min sclk falling edge to sync fall ignore 1 guaranteed by design and characterization, not production tested. 2 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v. timing diagram db0 db23 t 10 sclk sync din t 1 t 9 t 7 t 2 t 3 t 6 t 5 t 4 t 8 05856-002 figure 2. serial write operation
ad5624r/ad5644r/ad5664r rev. b | page 8 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja thermal impedance lfcsp_wd package (4-layer board) ja 61c/w msop package (4-layer board) ja 142c/w jc 43.7c/w reflow soldering peak temperature pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5624r/ad5644r/ad5664r rev. b | page 9 of 28 pin configuration and fu nction descriptions 1 v out a 10 v refin /v refout 2 v out b 9 v dd 3 gnd 8 din 4 v out c 7 sclk 5 v out d 6 sync ad5624r/ ad5644r/ ad5664r top view (not to scale) 05856-003 exposed pad tied to gnd on lfcsp package figure 3. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 2 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 3 gnd ground reference point for all circuitry on the part. 4 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 5 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 6 sync active low control input. this is the frame sy nchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the input shift register. data is transferred in on the falling edges of the next 24 clocks. if sync is taken high before the 24 th falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 7 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 50 mhz. 8 din serial data input. this device has a 24-bit shift register. da ta is clocked into the register on the falling edge of the serial clock input. 9 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 10 v refin /v refout the ad5624r/ad5644r/ad5664r have a common pin for reference input and reference output. when using the internal reference, this is the refere nce output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input.
ad5624r/ad5644r/ad5664r rev. b | page 10 of 28 typical performance characteristics code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 05856-004 v dd = v ref = 5v t a = 25c figure 4. ad5664r inl, external reference code inl error (lsb) 4 ?4 0 2500 5000 7500 10000 12500 15000 05856-005 ?3 ?2 ?1 0 1 2 3 v dd = v ref = 5v t a = 25c figure 5. ad5644r inl, external reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 05856-006 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c figure 6. ad5624r inl, external reference code dnl error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k 05856-007 v dd = v ref = 5v t a = 25c figure 7. ad5664r dnl, external reference dnl error (lsb) 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 05856-008 v dd = v ref = 5v t a = 25c code 0 2500 5000 7500 10000 12500 15000 figure 8. ad5644r dnl, external reference dnl error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 05856-009 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c figure 9. ad5624r dnl, external reference
ad5624r/ad5644r/ad5664r rev. b | page 11 of 28 code inl error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 05856-010 figure 10. ad5664r-5 inl, internal reference code inl error (lsb) 4 3 ?4 ?3 ?2 2 ?1 1 0 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd =5v v refout =2.5v t a = 25c 05856-011 figure 11. ad5644r-5 inl, internal reference code inl error (lsb) 1.0 0.8 0 ?1.0 ?0.8 ?0.6 0.6 ?0.4 ?0.2 0.4 0.2 0 1000 500 2000 1500 3500 3000 2500 4000 v dd =5v v refout =2.5v t a = 25c 05856-012 figure 12. ad5624r-5 inl, internal reference code dnl error (lsb) 1.0 0.8 0 ?1.0 ?0.6 ?0.8 ?0.4 0.6 ?0.2 0.4 0.2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd =5v v refout =2.5v t a =25c 05856-013 figure 13. ad5664r-5 dnl, internal reference code dnl error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 05856-014 figure 14. ad5644r-5 dnl, internal reference code dnl error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 05856-015 figure 15. ad5624r-5 dnl, internal reference
ad5624r/ad5644r/ad5664r rev. b | page 12 of 28 code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 05856-016 v dd = 3v v refout = 1.25v t a = 25c figure 16. ad5664r-3 inl, internal reference code inl error (lsb) 4 ?4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 05856-017 3 2 1 0 ?1 ?2 ?3 v dd = 3v v refout = 1.25v t a = 25c figure 17. ad5644r-3 inl, internal reference code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25c 05856-018 figure 18. ad5624r-3 inl, internal reference code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 05856-019 figure 19. ad5664r-3 dnl, internal reference code dnl error (lsb) 0.5 ?0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 3v v refout = 1.25v t a = 25c 05856-020 figure 20. ad5644r-3 dnl, internal reference code dnl error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25c 05856-021 figure 21. ad5624r-3 dnl, internal reference
ad5624r/ad5644r/ad5664r rev. b | page 13 of 28 temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 200 100 80 60 05856-022 min dnl max dnl max inl min inl v dd = v ref = 5v figure 22. inl error and dnl error vs. temperature v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 min dnl max dnl max inl min inl v dd = 5v t a = 25c 05856-023 figure 23. inl error and dnl error vs. v ref v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 min dnl max dnl max inl min inl t a = 25c 05856-024 figure 24. inl error and dnl error vs. supply temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 200 100 80 60 v dd = 5v gain error full-scale error 05856-025 figure 25. gain error and full-scale error vs. temperature temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 08 60 100 0 offset error zero-scale error 05856-026 figure 26. zero-scale error and offset error vs. temperature v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 gain error full-scale error 05856-027 figure 27. gain error and full-scale error vs. supply
ad5624r/ad5644r/ad5664r rev. b | page 14 of 28 v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 zero-scale error offset error t a = 25c 05856-028 figure 28. zero-scale error and offset error vs. supply i dd (ma) frequen c y 0 1 2 3 4 5 6 0.41 0.42 0.43 0.44 0.45 05856-029 v dd = 5.5v t a = 25c figure 29. i dd histogram with external reference, 5.5 v i dd (ma) frequen c y 0 1 2 3 4 5 6 0.92 0.94 0.96 0.98 05856-030 v dd = 5.5v t a = 25c figure 30. i dd histogram with internal reference, v refout = 2.5 v i dd (ma) frequency 0 1 2 3 5 4 6 8 7 0.39 0.40 0.41 0.42 0.43 05856-060 v dd = 3.6v t a = 25c figure 31. i dd histogram with external reference, 3.6 v i dd (ma) frequency 0 1 2 3 5 4 6 8 7 0.90 0.92 0.94 0.96 05856-061 v dd = 3.6v t a = 25c figure 32. i dd histogram with internal reference, v refout = 1.25 v current (ma) error voltage (v) 0.5 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 8 61 0 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current 0 5856-031 figure 33. headroom at rails vs. source and sink
ad5624r/ad5644r/ad5664r rev. b | page 15 of 28 current (ma) v out (v) 6 5 4 3 2 1 ?1 0 ?30 ?20 ?10 0 10 20 30 v dd = 5v v refout = 2.5v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 5856-046 figure 34. ad56x4r-5 sour ce and sink capability current (ma) v out (v) 4 ?1 0 1 2 3 ?30 ?20 ?10 0 10 20 30 v dd = 3v v refout = 1.25v t a = 25c zero scale full scale midscale 1/4 scale 3/4 scale 0 5856-047 figure 35. ad56x4r-3 sour ce and sink capability temperature (c) i dd (ma) 0.50 0.05 0.10 0.15 0.20 0.35 0.40 0.25 0.30 0.45 0 ?40 ?20 0 20 40 60 80 100 05856-063 t a = 25c v dd = v refin = 5v v dd = v refin = 3v figure 36. supply current vs. temperature time base = 4s/div v dd = v ref = 5v t a = 25c full-scale code change 0x0000 to 0xffff output loaded with 2k ? and 200pf to gnd v out = 909mv/div 1 05856-048 figure 37. full-scale settling time, 5 v ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25c v out v dd 1 2 max(c2) 420.0mv 05856-049 figure 38. power-on reset to 0 v 05856-050 v dd = 5v sync sclk v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 figure 39. exiting power-down to midscale
ad5624r/ad5644r/ad5664r rev. b | page 16 of 28 sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 05856-058 v dd = v ref = 5v t a = 25c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 to 0x7fff) figure 40. digital-to-analog glitch impulse (negative) sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 05856-059 v dd = v ref = 5v t a = 25c 5ns/sample number analog crosstalk = 0.424nv figure 41. analog crosstalk, external reference sample number v out (v) 2.456 2.458 2.460 2.462 2.464 2.466 2.468 2.470 2.472 2.474 2.476 2.478 2.480 2.482 2.484 2.486 2.488 2.490 2.492 2.494 2.496 0 50 100 150 350 400 200 250 300 450 512 05856-062 v dd = 5v v refout = 2.5v t a = 25c 5ns/sample number analog crosstalk = 4.462nv figure 42. analog crosstalk, 2.5 v internal reference 1 y axis = 2v/div x axis = 4s/div v dd = v ref = 5v t a = 25c dac loaded with midscale 05856-051 figure 43. 0.1 hz to 10 hz outp ut noise plot, external reference 5s/div 10v/div 1 v dd = 5v v refout = 2.5v t a = 25c dac loaded with midscale 05856-052 figure 44. 0.1 hz to 10 hz output noise plot, 2.5 v internal reference 4s/div 5v/div 1 v dd = 3v v refout = 1.25v t a = 25c dac loaded with midscale 05856-053 figure 45. 0.1 hz to 10 hz output noise plot, 1.25 v internal reference
ad5624r/ad5644r/ad5664r rev. b | page 17 of 28 frequency (hz) output noise (nv/ hz) 800 0 100 200 300 400 500 600 700 100 10k 1k 100k 1m v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25c midscale loaded 0 5856-054 capacitance (nf) time (s) 16 14 12 10 8 6 4 012 34567 9 81 0 v ref = v dd t a = 25c v dd = 5v v dd = 3v 0 5856-056 figure 46. noise spectral density, internal reference figure 48. settling time vs. capacitive load frequency (hz) amplitude (db) ? 20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k v dd = 5v t a = 25c dac loaded with full scale v ref = 2v 0.3v p-p 0 5856-055 frequency (hz) amplitude (db) 5 ?40 10k 100k 1m 10m ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 v dd = 5v t a = 25c 05856-057 figure 47. total harmonic distortion figure 49. multiplying bandwidth
ad5624r/ad5644r/ad5664r rev. b | page 18 of 28 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 4 . differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 7 . zero-code error zero-scale error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5664r because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero-code error is expressed in mv. a plot of zero-code error vs. temperature can be seen in figure 26 . full-scale error full-scale error is a measurement of the output error when full- scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error vs. temperature can be seen in figure 25 . gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. zero-code error drift this is a measurement of the change in zero-code error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5664r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change and is measured from the 24 th falling edge of sclk. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s, and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 40 ). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density this is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density can be seen in figure 46 . dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac (or soft power-down and power-up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv-s.
ad5624r/ad5644r/ad5664r rev. b | page 19 of 28 analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) using the command write to and update while monitor- ing the output of the victim channel that is at midscale. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db.
ad5624r/ad5644r/ad5664r rev. b | page 20 of 28 theory of operation digital-to-analog section the ad5624r/ad5644r/ad5664r dacs are fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 50 shows a block diagram of the dac architecture. dac register v dd gnd v out output amplifier (gain = +2) 05856-032 v refin resistor string ref figure 50. dac architecture because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? = n refout out d v v 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register: 0 to 4095 for ad5624r (12 bit). 0 to 16,383 for ad5644r (14 bit). 0 to 65,535 for ad5664r (16 bit). n is the dac resolution. resistor string the resistor string is shown in figure 51 . it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 33 and figure 34 . the slew rate is 1.8 v/s with a ? to ? full-scale settling time of 7 s. r r r r r to output amplifier 0 5856-033 figure 51. resistor string internal reference the ad5624r/ad5644r/ad5664r on-chip reference is off at power-up and is enabled via a write to a control register. see the internal reference setup section for details. the ad56x4r-3 has a 1.25 v, 5 ppm/c reference giving a full- scale output of 2.5 v. the ad56x4r-5 has a 2.5 v, 5 ppm/c reference giving a full-scale output of 5 v. the internal reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recommended that a 100 nf capacitor is placed between reference output and gnd for reference stability. external reference the v refin pin on the ad56x4r-3 and ad56x4r-5 allows the use of an external reference if the application requires it. the default condition of the on-chip reference is off at power-up. all devices (ad56x4r-3 and the ad56x4r-5) can be operated from a single 2.7 v to 5.5 v supply. serial interface the ad5624r/ad5644r/ad5664r have a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as with most dsps. see for a timing diagram of a typical write sequence. figure 2 the write sequence begins by bringing the sync line low. data from the din line is clocked into the 24-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the ad5624r/ad5644r/ad5664r compat- ible with high speed dsps. on the 24 th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in dac register contents and/or a change in the mode of operation.
ad5624r/ad5644r/ad5664r rev. b | page 21 of 28 at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 15 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation. as mentioned previously, it must, however, be brought high again just before the next write sequence. input shift register the input shift register is 24 bits wide (see figure 52 ). the first two bits are dont care bits. the next three are the command bits, c2 to c0 (see table 8 ), followed by the 3-bit dac address, a2 to a0 (see table 9 ), and then the 16-, 14-, 12-bit data-word. the data-word comprises the 16-, 14-, 12-bit input code followed by 0, 2, or 4 dont care bits, for the ad5664r, ad5644r, and ad5624r, respectively (see figure 52 , figure 53 , and figure 54 ). these data bits are transferred to the dac register on the 24 th falling edge of sclk. table 8. command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n, update all (software ldac) 0 1 1 write to and update dac channel n 1 0 0 power down dac (power-up) 1 0 1 reset 1 1 0 ldac register setup 1 1 1 internal reference setup (on/off ) table 9. address command a2 a1 a0 address (n) 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 1 1 all dacs sync interrupt in a normal write sequence, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24 th falling edge. however, if sync is brought high before the 24 th falling edge, then this acts as an interrupt to the write sequence. the input shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see ). figure 55 x x c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05856-034 figure 52. ad5664r input shift register contents x x c2 c1 c0 a2 a1 a0 xx d11 d10 d13 d12 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05856-035 figure 53. ad5644r input shift register contents x x c2 c1 c0 a2 a1 a0 xxxx d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 db23 (msb) db0 (lsb) command bits address bits data bits 05856-036 figure 54. ad5624r input shift register contents din db23 db23 db0 db0 valid write sequence, output updates on the 24 th falling edge s yn c sclk invalid write sequence: sync high before 24 th falling edge 05856-037 figure 55. sync interrupt facility
ad5624r/ad5644r/ad5664r rev. b | page 22 of 28 power-on reset the ad5624r/ad5644r/ad5664r family contains a power-on reset circuit that controls the output voltage during power-up. the output of the ad5624r/ad5644r/ad5664r dacs powers up to 0 v and the output remains there until a valid write sequence is made to the dacs. this is useful in applications where it is important to know the state of the output of the dacs while they are in the process of powering up. software reset the ad5624r/ad5644r/ad5664r contain a software reset function. command 101 is reserved for the software reset function (see table 8 ). the software reset command contains two reset modes that are software programmable by setting bit db0 in the control register. table 10 shows how the state of the bit corresponds to the software reset modes of operation of the devices. table 12 shows the contents of the input shift register during the software reset mode of operation. table 10. software reset modes for the ad5624r/ad5644r/ad5664r db0 registers reset to 0 0 dac register input shift register 1 (power-on reset) dac register input shift register ldac register power-down register internal reference setup register power-down modes the ad5624r/ad5644r/ad 5664r contain four separate modes of operation. command 100 is reserved for the power-down function (see table 8 ). these modes are software programmable by setting two bits (db5 and db4) in the control register. table 11 shows how the state of the bits corresponds to the mode of operation of the device. all dacs (dac d to dac a) can be powered down to the selected mode by setting the correspond- ing four bits (db3, db2, db1, and db0) to 1. by executing the same command 100, any combination of dacs can be powered up by setting the bits (db5 and db4) to normal operation mode. to select which combination of dac channels to power-up, set the corresponding four bits (db3, db2, db1, and db0) to 1. see table 13 for contents of the input shift register during power-down/power-up operation. modes of operation for the ad5624r/ad5644r/ db5 db4 operating mode table 11. ad5664r 0 0 normal operation 0 1 power-down mode: 1 k to gnd 1 0 power-down mode: 100 k to gnd 1 1 power-down mode: three-state when bit db5 and bit db4 are set to 0, the part works normally with its normal power consumption of 450 a at 5 v. however, for the three power-down modes, the supply current falls to 480 na at 5 v (200 na at 3 v). not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this allows the output impedance of the part to be known while the part is in power-down mode. the outputs can either be connected internally to gnd through a 1 k resistor, or left open-circuited (three-state) as shown in figure 56 . resistor network v out resistor string dac power-down circuitry amplifier 05856-038 figure 56. output stage during power-down the bias generator, the output amplifier, the resistor string, and other associated linear circuitry are shutdown when power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 4 s for v dd = 5 v and for v dd = 3 v (see figure 39 ). table 12. 24-bit input shift register contents for software reset command db23 to db22 (msb) db 21 db20 db19 db18 db17 db16 db15 to db1 db0 (lsb) x 1 0 1 x x x x 1/0 dont care command bits (c2 to c0) address bits (a2 to a0) dont care determines software reset mode table 13. 24-bit input shift register contents of powe r-down/power-up operation for the ad5624r/ad5644r/ad5664r db23 to db22 (msb) db21 db20 db 19 db18 db17 db16 db15 to db6 db5 db4 db3 db2 db1 db0 (lsb) x 1 0 0 x x x x pd1 pd0 dac d dac c dac b dac a dont care command bits (c2 to c0) address bits (a2 to a0) dont care dont care power-down mode power-down/power-up channel selection, set bit to 1 to select channel
ad5624r/ad5644r/ad5664r rev. b | page 23 of 28 ns- sed erface is useful if the user requires he controlled by the ldac function. ch e nd db0). w, the corresponding dac s can change state egisters. when the registers e transparent and t ut registers are nsferred to them on th th sclk pulse. havin ldac function the ad5624r/ad5644r/ad5664r dacs have double- buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is tra ferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code u by the resistor strings. the double-buffered int simultaneous updating of all dac outputs. the user can write to three of the input registers individually and then write to t remaining input register, updating all dac registers simulta- neously. command 010 is reserved for this software ldac. access to the dac registers is the ldac register contains two modes of operation for ea dac channel. the dac channels are selected by setting th bits of the 4-bit ldac register (db3, db2, db1, a command 110 is reserved for setting up the ldac register. when the ldac bit register is set lo registers are latched and the input register without affecting the contents of the dac r bit register is set hi ldac com gh, however, the dac the inp be he contents of tra e falling edge of the 24 this is equivalent to g an ldac h ardwa re pin tied perma- lected is, synchronous pdate mode. see table 1 ster mode of peration. see table 16 fo hift register uring the ldac register peration n ently low for the se dac channel, that regi u 4 for the ldac o r contents of the input s d setup command. this flexibility is useful in applications where the user wants to update select channels simultaneously, while the rest of the channels update synchronously. table 14. ldac register mode of operation ldac bits (db3 to db0) ldac mode of o 0 normal operation (default), dac register update is controlled by write command. 1 the dac regis ters are updated after new e. data is read in on the falling edge of the 24 th sclk puls in tern l ref e on-chi eferen reference (db0) action a erence setup th p r ce is off at power-up by default. this can be turned on or off by setting a software programmable bit, db0, in the control register. table 15 shows how the state of the bit corresponds to the mode of operation. command 111 is reserved for setting up the internal reference (see table 8 ). table 16 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup. table 15. reference setup register internal reference setup register 0 reference off (default) 1 reference on p command for the ad5624r/ad5644r/ad5664r db16 table 16. 24-bit input shift register contents for ldac setu db23 to db22 (msb) db21 db20 db19 db18 db17 db15 to db4 db 3 db2 db1 db0 (lsb) x 1 1 0 x x x x dac d dac c dac b dac a dont care command bits (c2 to c0) address b (a2 to a0); don its t care dont care set bit to 0 or 1 for required mode of operation on respective channel table 17. 24-bit input shift register contents for internal re db23 to db22 ference setup command sb) db21 db20 db19 db18 db17 db16 db15 to db1 db0 (lsb) (m x 1 1 1 x x x x 1/0 dont care command bits (c2 to c0) address bits (a2 to a0 ) dont care reference setup register
ad5624r/ad5644r/ad5664r rev. b | page 24 of 28 r interfacing 53x o essor communications. using sport0 for microprocesso ad5624r/ad5644r/ad5664r to black fin adsp-bf interface figure 57 shows a serial interface between the ad5624r/ ad5644r/ad5664r and the black fin? adsp-bf53x micro- processor. the adsp-bf53x processor family incorporates tw dual-channel synchronous serial ports, sport1 and sport0, for serial and multiproc to connect to the ad5624r/ad5644r/ad5664r, the setup the interface is that the dt0pri drives the din pin of the ad5624r/ad5644r/ad5664r, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. ad5624r/ ad5644r/ ad5664r 1 adsp-bf53x 1 sync tfs0 din dtopri sclk tsclk0 1 additional pins omitted for clarity. 05856-039 figure 57. black fin adsp-bf53x interface to ad5624r/ad5644r/ad566 ad5624r/ad5644r/ad5664r to 68hc11/68l11 interface 4r figure 58 shows a serial interface between the ad5624r/ ad5644r/ad5664r and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5624r/ ad5644r/ad5664r, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup onditions for correct operation of this interface are that the c11/68l11 is configured with its cpol bit as 0 and its c 68h cpha bit as 1. when data is transmitted to the dac, the sync line is taken low as descri (pc7). when the 68hc11/68l11 is configured bed previo ta in m utp lid on the falling ge of s . seria ta from he 68h 1/ nsmitted in 8 nly eight fallin edges occurring in the tran ta is tran first. to load data to the ad5624r/ad5644r/ad5664r, pc7 is ation is performed to the dac; pc7 is taken he end of thi ure usly, da appear g on the osi o ut is va ed ck l da t c1 68l11 is tra -bit bytes with o smit cycle. da g clock smitted msb left low after the first eight bits are transferred, and a second serial write oper high at t s proced . 68hc11/68l11 sync 1 pc7 sclk sck din mosi 1 additional pins omitted for clarity. ad5624r/ ad5644r/ ad5664r 1 05856-040 figure 58. 68hc11/68l11 interface to ad5624r/ad5644r/ad5664r /80l51 microcontroller. the /80l51 drives xd drives the f the par ad5624r/ad5644r/ad5664r to 80c51/80l51 interface figure 59 shows a serial interface between the ad5624r/ ad5644r/ad5664r and the 80c51 setup for the interface is that the txd of the 80c51 ad5624r/ad5644r/ad5664r, while r sclk of the serial data line o t. the sync signal is derived from a bit- rammable pin on th when data is transmitted .3 is taken low. the 80 only; thus, only eight fall to load data to the dac, er the first eight bits are itiated to transmit the owing the completion of prog e port. in this case, port line p3.3 is used. to the ad5624r/ad5644r/ad5664r, p3 c51/80l51 transmits data in 8-bit bytes ing clock edges occur in the transmit cycle. p3.3 is left low aft transmitted, and a second write cycle is in second byte of data. p3.3 is taken high foll this cycle. the 80c51/80l51 outputs the serial data in lsb first format. the ad5624r/ad5644r/ad5664r must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. 80c51/80l51 1 sync p3.3 sclk txd din rxd 1 additional ad5624r/ ad5644r/ ad5664r 1 pins omitted for clarity. 05856-041 ure 59. 80c51/80l5 to ad5624r/ad5644r/ad5664r 5624r/ad5644r/ ire interface gure 60 shows an inter he ad5624r/ad5644r/ d5664r and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5624r/ad5644r/ad5664r on the rising fig 1 interface ad ad5664r to microw fi face between t a edge of the sk. microwire 1 sy nc cs sclk sk din so 1 additi onal pins omitted for clarity. ad5624r/ ad5 / ad5 05856-042 figure 60. microwire interface to ad5624r/ad5644r/ad5664r 644r 664r 1
ad5624r/ad5644r/ad5664r rev. b | page 25 of 28 applications using a reference as a power supply for the ad5624r/ad5644r/ad5664r because the supply current required by the ad5624r/ad5644r/ ad5664r is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure 61). this is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad5624r/ad5644r/ad5664r (see figure 59). if the low dropout ref195 is used, it must supply 450 a of current to the ad5624r/ad5644r/ad5664r with no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k load on the dac output) is 450 a + (5 v/5 k) = 1.45 ma the load regulation of the ref195 is typically 2 ppm/ma, resulting in a 2.9 ppm (14.5 v) error for the 1.45 ma current drawn from it. this corresponds to a 0.191 lsb error. 3-wire serial interface sync sclk din 15 v 5v v out = 0v to 5v v dd ref195 ad5624r/ ad5644r/ ad5664r 05856-043 figure 61. ref195 as power supply to the ad5624r/ad5644r/ad5664r bipolar operation using the ad5624r/ad5644r/ad5664r the ad5624r/ad5644r/ad5664r have been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 62. the circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd out 536,65 where d represents the input code in decimal (0 to 65,536). with v dd = 5 v, r1 = r2 = 10 k, v5 536,65 10 ? ? ? ? ? ? ? = d v out this is an output voltage range of 5 v, with 0x0000 corre- sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. 3-wire serial interface r2 = 10k ? +5v ?5v ad820/ op295 +5v ad5624r/ ad5644r/ ad5664r v dd v out r1 = 10k ? 5v 0.1f 10f 05856-044 figure 62. bipolar operation with the ad5624r/ad5644r/ad5664r using ad5624r/ad5644r/ad5664r with a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common- mode voltages that might occur in the area where the dac is functioning. isocouplers provide isolation in excess of 3 kv. the ad5624r/ad5644r/ad5664r use a 3-wire serial logic interface, so the adum130x 3-channel digital isolator provides the required isolation (see figure 63). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5624r/ad5644r/ad5664r. 0.1f 5v regulator gnd din sync sclk power 10f sdi sclk data ad5624r/ ad5644r/ ad5664r v out v ob v oa v oc v dd v ic v ib v ia adum1300 05856-045 figure 63. ad5624r/ad5644r/ad5664r with a galvanically isolated interface
ad5624r/ad5644r/ad5664r rev. b | page 26 of 28 passing and grounding y e ad5624r/ ries inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low imped- ance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side not power supply by when accuracy is important in a circuit, it is helpful to carefull consider the power supply and ground return layout on the board. the printed circuit board containing th ad5644r/ad5664r should have separate analog and digital sections, each having its own area of the board. if the ad5624r/ ad5644r/ad5664r are in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5624r/ad5644r/ad5664r. the power supply to the ad5624r/ad5644r/ad5664r should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitor is the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and effective se of the board is dedicated to the ground plane only and th e signal traces are placed on the solder side. however, this is always possible with a 2-layer board.
ad5624r/ad5644r/ad5664r rev. b | page 27 of 28 outline dimensions 031208-b top view 10 1 6 5 0.30 0.23 0.18 pin 1 index area 3.00 bsc sq exposed pad (bottom view) seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 2 0 ) 0.50 0.40 0.30 figure 64. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 65. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters
ad5624r/ad5644r/ad5664r rev. b | page 28 of 28 odel temperature ra ac ordering guide m nge curacy internal reference package description package option branding ad5624rbcpz-3r2 1 ?40c to +105c 1 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d7l ad5624rbcpz-3reel7 1 ?40c to +105c 1 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d7l ad5624rbcpz-5r2 1 ?40c to +105c 1 lsb inl 2.5 v 10-lead lfcsp_wd cp-10-9 dbz ad5624rbcpz-5reel7 1 ?40c to +105c 1 lsb inl 2.5 v 10-lead lfcsp_wd cp-10-9 dbz ad5624rbrmz-3 1 ?40c to +105c 1 lsb inl 1.25 v 10-lead msop rm-10 d7l ad5624rbrmz-3reel7 1 ?40c to +105c 1 lsb inl 1.25 v 10-lead msop rm-10 d7l ad5624rbrmz-5 1 ?40c to +105c 1 lsb inl 2.5 v 10-lead msop rm-10 d7v ad5624rbrmz-5reel7 1 ?40c to +105c 1 lsb inl 2.5 v 10-lead msop rm-10 d7v ad5644rbrmz-3 1 ?40c to +105c 4 lsb inl 1.25 v 10-lead msop rm-10 d7e ad5644rbrmz-3reel7 1 ?40c to +105c 4 lsb inl 1.25 v 10-lead msop rm-10 d7e ad5644rbrmz-5 1 ?40c to +105c 4 lsb inl 2.5 v 10-lead msop rm-10 d7d AD5644RBRMZ-5REEL7 1 ?40c to +105c 4 lsb inl 2.5 v 10-lead msop rm-10 d7d ad5664rbcpz-3r2 1 ?40c to +105c 16 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d73 ad5664rbcpz-3reel7 1 ?40c to +105c 16 lsb inl 1.25 v 10-lead lfcsp_wd cp-10-9 d73 ad5664rbrmz-3 1 ?40c to +105c 16 lsb inl 1.25 v 10-lead msop rm-10 d73 ad5664rbrmz-3reel7 1 ?40c to +105 ad msop rm-10 d73 c 16 lsb inl 1.25 v 10-le ad5664rbrmz-5 1 ?40c to +105c 16 lsb inl 10-lead msop rm-10 d75 2.5 v ad5664rbrmz-5reel7 1 ?40c to +105c 10-lead msop rm-10 d75 16 lsb inl 2.5 v e val-ad5664rebz 1 evaluation board 1 z = rohs compliant part. ?2006C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05856-0-4/08(b)

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